Technical Field
The present disclosure relates to integrated circuits, and more particularly, to source/drain terminal contacts which have been implanted with a species, and methods of forming the same.
Related Art
Advanced manufacturing of integrated circuits requires formation of individual circuit elements, e.g., field-effect-transistors (FETs) and the like based on specific circuit designs. A FET generally includes source, drain, and gate terminals. The gate terminal is placed between the source and drain terminals. Transistors may be formed over a substrate and may be electrically isolated with an insulating dielectric layer, e.g., inter-level dielectric layer. Contacts may be formed to each of the source, drain, and gate terminals through the dielectric layer in order to provide electrical connection between the transistors and other circuit elements that may be formed subsequent to the transistor in other metal levels.
Conventionally, contacts to the source and drain terminals are formed by forming an opening within the overlying insulating dielectric layer(s) to expose the source and drain terminals. Subsequently, liner layers, e.g., titanium, and a metallization layer may be formed within the opening to fill the opening. Further, the process may include performing an anneal to create a silicide, i.e., silicon metal alloy, at the bottom surface of the opening and a top surface of the source and drain terminals thereby creating a surface for the contact connection. The silicide that is formed in aforementioned manner called liner silicide. The contact may be planarized evenly with a top surface of the dielectric layer.
The annealing process for this conventional silicidation process is limited to a temperature which does not cause damage to the gate terminal and the elements therein. However, silicide formation may require a high temperature in order to be performed. Therefore, there is a struggle to reach a temperature high enough to create the silicide for the source and drain contact without causing damage to the gate terminal. Furthermore, in some instances the silicide may not actually be formed leaving an intermetallic alloy on the active areas; i.e. source and drain terminals. The resultant silicide may have a better contact resistance performance on n-type FET (NFET) than p-type FET (PFET), which can be attributed to the difficulties of desired silicide formation on PFET as opposed to NFET.